Question
During the physical design stage of VLSI, a buffered H-tree is planned so that this signal is delivered to chip components with minimal skew. For 10 points each:
[10m] Name this signal whose frequency is directly proportional to the dynamic power consumed by a CPU.
ANSWER: clock signal
[10h] This communication paradigm moves beyond clock trees when they consume too much power or become overly complex. This paradigm, a form of globally asynchronous, locally synchronous design, replaces traditional buses and crossbars with some packet-switched topology.
ANSWER: network-on-chip [or NoC or network-on-a-chip; or on chip networks; reject “system on a chip”]
[10e] Networks-on-chip were designed in response to the amount of these devices on chips increasing, while clock frequency has plateaued. The number of these devices on a microchip doubles every two years per Moore’s law.
ANSWER: transistors [accept any type of transistor; prompt on semiconductor devices]
Data
| Team | Opponent | Part 1 | Part 2 | Part 3 | Total |
|---|---|---|---|---|---|
| Chicago A | Georgia Tech A | 10 | 0 | 10 | 20 |